Correcting or modifying a designed logic circuit (hereinafter termed “logic modification”) of a semiconductor integrated circuit device during or after designing the device is often required owing to design error, change in process conditions, and so forth.
In such case, an optimum transistor layout can be obtained after the logic modification by adding the newly required transistors. This method, however, has a disadvantage in that process correction is required as far back as the diffusion process because transistors are newly added. This means that almost all photomasks used during the photolithography processes must be changed and, therefore, not only does the manufacturing cost increase markedly but the time required to complete the modification becomes long. Recent years have seen not only an increase in the cost of photomasks owing to advances in fine processing technology but also a need for shorter turnaround time. This conventional method is therefore not practical in the light of current circumstances.
To solve this problem, Japanese patent application laid open No. H5-198680 discloses a method that provides the spare transistors needed for logic modification in advance. According to this method, the logic modification can be performed without changing the photomasks used during the diffusion process and the gate electrode forming process. However, this method also has a disadvantage in that the process correction is required as far back as the gate electrode forming process and almost all of the successive processes have to be changed. This results in increased cost and longer turnaround time.
On the other hand, Japanese patent application laid open No. 2002-319665, which relates to a semiconductor integrated circuit of the gate array type, discloses a method in which wiring patterns are independently provided above the CMOS basic cells in advance in order to mitigate the wiring density. However, this method is not sufficient for avoiding a marked increase in cost and turnaround time because it has a disadvantage in that process correction is required as far back as the process of forming the contact holes used to connect to the wiring patterns.
Although other logic modification methods for the semiconductor integrated circuit device are disclosed in Japanese patent application laid open No. 2000-299382, Japanese patent application laid open No. 2000-236063, and Japanese patent application laid open No. H6-216247, it is impossible or very difficult to add a complex logic circuit by these methods.
As set out above, according to the prior art it is difficult to avoid marked increase in cost and turnaround time when logic modification of a semiconductor integrated circuit device is required, particularly when addition of complex logic circuits is required, during or after designing the device.